Digital computing systems often express data in "scientific notation" or "floating point" format. In scientific notation, a number consists of a mantissa and an exponent. The value of the number is the product of the mantissa, the radix of the numbering system and the exponent if the exponent is positive. Conversely, the value of the number is the quotient of the mantissa and the product of the radix and the exponent if the exponent is negative. In digital computing systems, the radix of the most common numbering system is two.
Digital computing systems often require that a mantissa of a binary number have a one in its leading digit, or most significant bit. The exponent is then adjusted so that value, as described above, is equal to the value of the number as originally expressed. Digital computing systems make this requirement for several reasons, including improved data precision, implementation speed and industry norms.
Normalizers are a class of devices that receive data expressed in scientific notation and adjust the mantissa and exponent such that the mantissa has a one in the leading digit. Known normalizers perform their function in a number of serialized steps. For instance, a known normalizer might receive a sixty-four bit un-normalized mantissa and output a normalized mantissa in three stages.
In the first stage of a known normalizer, the normalizer determines if the leading one is in the first sixteen digits, is in one of the seventeenth through thirty-second digits, is in one of the thirty-third through forty-eighth digits, or is in one of the forty-ninth through sixty-fourth digits. The result of this first determination controls the output of a first four-to-one, sixty-four-bit multiplexer. The first multiplexer outputs either the input value, the input shifted sixteen digits and concatenated with sixteen zeros, the input shifted thirty-two digits and concatenated with thirty-two zeros, or the input shifted forty-eight digits and concatenated with forty-eight zeros. After this stage, the mantissa's leading one is in one of the first sixteen digits.
In the second stage of the known normalizer, the normalizer determines if the leading one is in the first four digits of the first stage output, is in one of the fifth through eighth digits, is in one of the ninth through twelfth digits, or is in one of the thirteenth through sixteenth digits. The result of this second determination controls the output of a second four-to-one, sixty-four-bit multiplexer. The second multiplexer outputs either the output of the first multiplexer, the output of the first multiplexer shifted four digits and concatenated with four zeros, the output of the first multiplexer shifted eight digits and concatenated with eight zeros, or the output of the first multiplexer shifted twelve digits and concatenated with twelve zeros. After this stage, the mantissa's leading one is in one of the first four digits.
In the third stage of the known normalizer, the normalizer determines if the leading one is in the first digit of the second stage output, is in the second digit, is in the third digit, or is in the fourth digit. The result of this third determination controls the output of a third four-to-one, sixty-four-bit multiplexer. The third multiplexer outputs either the output of the second multiplexer, the output of the second multiplexer shifted one digit and concatenated with one zero, the output of the second multiplexer shifted two digits and concatenated with two zeros, or the output of the second multiplexer shifted three digits and concatenated with three zeros. After this stage, the mantissa's leading one is in the first digit.
The critical speed path of a known three-stage normalizer is the propagation delay through three four-to-one multiplexers and three sets of decode circuits because the three determinations described above require intermediate shift results.